A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold

A pipelined ADC architecture for use in sub-sampled systems which is power scalable in relation to its down sampled bandwidth is presented. The ADC uses a technique to eliminate the front-end sample hold, thereby reducing power consumption. The technique allows for a power savings of 20% compared to a previous design. A method to improve the settling behavior of rapid power-on opamps is also presented. Measured results in a 1.8 V 0.18 CMOS process verify the removal of the front-end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With 50 MS/s, for the SNDR is 51.5 dB, and with 4.55 MS/s for the SNDR is 52.2 dB.