DocumentCode :
773366
Title :
An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage
Author :
Ahmed, Imran ; Johns, David A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Toronto, ON
Volume :
43
Issue :
7
fYear :
2008
fDate :
7/1/2008 12:00:00 AM
Firstpage :
1626
Lastpage :
1637
Abstract :
A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 104 clock cycles.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; digital-analogue conversion; error correction; pipeline processing; CMOS process; DAC error correction; analogue-digital conversion; calibration; digital background scheme; digital-analogue conversion; multibit pipeline stage; pipelined ADC; size 0.18 mum; voltage 1.8 V; word length 11 bit; Bandwidth; Calibration; Error correction; Fabrication; Harmonic distortion; Linearity; MIM capacitors; OFDM; Pipelines; Sampling methods; ADC; CMOS; DAC; analog-to-digital conversion; background; calibration; capacitor mismatch; dual-ADC; missing codes; pipeline; rapid; split-ADC;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2008.923724
Filename :
4550628
Link To Document :
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