• DocumentCode
    773404
  • Title

    A note on "A high-speed residue-to-binary converter for three-moduli (2k 2k - 1, 2k-1 - 1) RNS and a scheme for its VLSI implementation"

  • Author

    Wang, Wei ; Swamy, M.N.S. ; Ahmad, M.O. ; Wang, Yuke

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
  • Volume
    49
  • Issue
    3
  • fYear
    2002
  • fDate
    3/1/2002 12:00:00 AM
  • Firstpage
    230
  • Lastpage
    230
  • Abstract
    In the title paper (W. Wang et al., ibid. vol. 47, pp. 1576-1581, 2000), an error occurred in the column corresponding to the time-complexity product of the proposed residue-to-binary converter and the previous converter. In this note, we provide correct figures for the time-complexity product (AT). In addition, we give the values for the complexity-time square product (AT2) for these two converters
  • Keywords
    VLSI; circuit complexity; digital signal processing chips; residue number systems; AND gates; VLSI implementation; complexity-time square product; critical path delay; high-speed residue-to-binary converter; three-moduli RNS; time-complexity product; Adders; Circuits; Computer science; Delay; Digital signal processing; Signal processing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1057-7130
  • Type

    jour

  • DOI
    10.1109/TCSII.2002.1013871
  • Filename
    1013871
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=773404