C-configurability and built-in-test of reconfigurable processor array interconnection networks

A general-purpose interconnection switch applicable to reconfigurable architectures is described. The switch has been used in the design of reconfigurable architectures and in processor arrays that require reconfigurable interconnections. The reconfigurable switch has the desirable properties that it is both scalable and C-testable. Furthermore, the switch is shown to be C-configurable: that is, the number of configurations required to test a network of switches is independent of the size of the network. Criteria are given for selecting built-in-test (BIT) techniques and implementations for reconfigurable architectures. Algorithms for generating configuration values and test data are presented. The BIT implementation is presented and analyzed and is shown to provide 100% fault coverage for single S-A-0, S-A-1, bridging, and high-impedance, permanent combinational faults