Multiple-valued logic network using quantum-device-oriented superpass gates and its minimisation

A superpass-transistor (SPT) model is presented as a quantum-device candidate for future VLSI systems based on multiple-valued logic (MVL). A conceptual SPT structure based on the ideas of a lateral-resonant-tunnelling quantum-dot transistor (LQT) and a heterostructure FET is described. An important feature of the SPT is its capability of MVL signal detection and generation. A superpass gate (SP gate) corresponding to a single SPT is defined and is demonstrated to be a universal logic module for implementing highly compact multiple-valued VLSI systems. An algorithm suitable for synthesising minimal series-parallel SP-gate networks for MVL functions with many variables is proposed. The network allows both constants and variables as its pass inputs; accordingly, υ-subfunctions, where υ can be a constant or a variable, are defined. SP implicants, SP subimplicants and the consensus between SP subimplicants are also defined. The algorithm first generates all prime SP subimplicants from υ-subfunctions by using the consensus operation, then derives all prime SP implicants by using the implication operation, and finally selects an optimal set of prime SP implicants to cover the function by using existing methods