Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

Author

Chatterjee, Bhaskar ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Ont., Canada

Volume

13

Issue

11

fYear

2005

Firstpage

1296

Lastpage

1304

Abstract

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.

Keywords

CMOS digital integrated circuits; design for testability; fault diagnosis; integrated circuit design; integrated circuit testing; low-power electronics; 1.7 GHz; 180 nm; 32 bit; CMOS technology; arithmetic and log unit; automatic test equipment; clock frequency; delay faults; delay-fault testability; delay-fault-testable ALU; design-for-test scheme; digital circuits; flip-flops; leakage power; microprocessor testing; very large scale integration; Arithmetic; Automatic test equipment; Automatic testing; CMOS technology; Clocks; Degradation; Delay; Design for testability; Fault detection; Frequency; Design for testability; digital circuits; flip-flops; microprocessor testing; very large scale integration (VLSI);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2005.859563

Filename

1564082