DocumentCode
774641
Title
Optimisation of high-performance gates in AlGaAs/GaAs quantum-well technology
Author
Bushehri, E. ; Bratov, V. ; Thiede, A. ; Staroselsky, V. ; Heuser, O. ; Malamud, I.
Author_Institution
Microelectron. Centre, Middlesex Univ., London, UK
Volume
142
Issue
6
fYear
1995
fDate
12/1/1995 12:00:00 AM
Firstpage
394
Lastpage
398
Abstract
Ultra-high-speed logic gates are proposed using heterostructure field-effect transistors. A simple noise margin optimisation method is applied to improve the performance in terms of noise margin and delay. A 16-bit binary carry look-ahead adder is then used as a demonstrator circuit to show the advantages of the logic gates over the standard direct coupled FET logic implementation
Keywords
III-V semiconductors; adders; aluminium compounds; carry logic; combinational circuits; delays; field effect logic circuits; field effect transistors; gallium arsenide; integrated circuit noise; logic gates; semiconductor quantum wells; 16 bit; AlGaAs-GaAs; binary carry look-ahead adder; delay; heterostructure field-effect transistors; high-performance gates; noise margin optimisation method; quantum-well technology; ultra-high-speed logic gates;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:19952257
Filename
487950
Link To Document