Title :
Hierarchical mapping of spot defects to catastrophic faults-design and applications
Author :
Gaitonde, Dinesh D. ; Walker, D.M.H.
Author_Institution :
Low Power & Timing Group, Motorola Inc., Tempe, AZ, USA
fDate :
5/1/1995 12:00:00 AM
Abstract :
This paper describes the defect to fault mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164 K transistors. Test quality analysis results are given for an adder module
Keywords :
CMOS integrated circuits; adders; integrated circuit design; integrated circuit testing; integrated circuit yield; probability; quality control; CMOS designs; IC defect testing; adder module; catastrophic faults; defect to fault mapper; design hierarchy; hierarchical mapping; integrated circuit test quality analysis; manufacturing process; probability; test quality analysis; yield prediction; Application specific integrated circuits; Circuit analysis; Circuit faults; Circuit testing; Integrated circuit testing; Manufacturing processes; Probability; Statistics; Virtual manufacturing; Yield estimation;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
