A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond

Author

Yamagata, Tadato ; Sato, Hirotoshi ; Fujita, Kore-aki ; Nishimura, Yasumasa ; Anami, Kenji

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

31

Issue

2

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

195

Lastpage

201

Abstract

This paper describes a distributed globally replaceable redundancy (DGR) scheme which achieves a higher optimization of the trade-off between yield enhancement and chip area penalty. A newly developed yield simulator using the Monte Carlo method has estimated the effectiveness of the DGR scheme in a quantitative manner. The new redundancy scheme is expected to enhance the yield by several times compared with conventional redundancy in the early stages of production. The DGR scheme has been successfully implemented in an experimental 4 Mb SRAM with a 3.0% area overhead and an average redundancy usage efficiency of 61% has been obtained in repaired pass chips

Keywords

Monte Carlo methods; SRAM chips; ULSI; circuit optimisation; integrated circuit yield; redundancy; semiconductor process modelling; 0.5 micron; 4 Mbit; 61 percent; Monte Carlo method; SRAM; chip area; chip repair; distributed globally replaceable redundancy; optimization; production; sub-half-micron ULSI memories; usage efficiency; yield simulator; Acceleration; Circuits; Costs; Investments; Mass production; Random access memory; Research and development; Semiconductor memory; Ultra large scale integration; Yield estimation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.487996

Filename

487996