A time digitizer CMOS gate-array with a 250 ps time resolution

Author

Arai, Yasuo ; Ikeno, Masahiro

Author_Institution

KEK, Nat. Lab. for High Energy Phys., Ibaraki, Japan

Volume

31

Issue

2

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

212

Lastpage

220

Abstract

A pipelined time digitizer CMOS gate-array has been developed using 0.5 μm Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion

Keywords

CMOS integrated circuits; analogue-digital conversion; logic arrays; timing circuits; 0.5 micron; 10 mHz to 50 MHz; 250 ps; asymmetric ring oscillator; dual-port memories; encoding circuits; phase-locked loop circuit; pipelined time digitizer CMOS gate-array; sea-of-gate technology; time memory cell; time resolution; timing signals; CMOS technology; Circuit testing; Clocks; Frequency; Phase locked loops; Ring oscillators; Semiconductor device measurement; Signal generators; Signal resolution; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.487998

Filename

487998