A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier

Author

Larsson-Edefors, Per

Author_Institution

Dept. of Phys., Linkoping Univ., Sweden

Volume

31

Issue

2

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

230

Lastpage

239

Abstract

This paper presents a two´s complement high-speed twin-pipe serial/parallel multiplier architecture which produces y=cd, where c is the parallel coefficient and d is the serial data. The multiplier is based on the twin pipeline (twin-pipe) concept, in which two data bits are processed each clock cycle. The high serial data throughput rate is mainly due to the use of: 1) a novel twin-pipe architecture, 2) new twin-pipe adder types, and 3) a new multiplier circuit structure. A 4-bit high-speed twin-pipe serial/parallel multiplier, on an active area of 0.224 mm², has been designed and fabricated in a 1.0-μm N-well double-metal single-poly CMOS process. Testing of the multiplier shows that the maximal serial data throughput rate is 965 Mb/s at V_dd=5 V

Keywords

CMOS logic circuits; multiplying circuits; parallel processing; pipeline arithmetic; 1 micron; 5 V; 965 Mbit/s; N-well CMOS process; double-metal single-poly process; high serial data throughput rate; high-speed multiplier architecture; serial/parallel multiplier; twin pipeline concept; twin-pipe adder types; two´s complement type; Adders; Bandwidth; CMOS process; CMOS technology; Circuit testing; Clocks; Data processing; Hardware; Pipelines; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.488000

Filename

488000