Title :
VLSI implementation for low-complexity full-search motion estimation
Author :
Hsia, Shih-Chang
Author_Institution :
Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Taiwan
fDate :
7/1/2002 12:00:00 AM
Abstract :
Although many ASICs for motion estimation have been developed, either the chip complexity is too high or the optimal accuracy was not achieved. In this study, an adaptive full-search algorithm is presented to reduce the searching complexity with a temporal correlation approach. The efficiency of the proposed full search can be promoted about 5-10 times in comparison with the conventional full search while the searching accuracy remains intact. Based on the adaptive full-search algorithm, a real-time VLSI chip is regularly designed by using the module base. For MPEG-2 applications, the computational kernel only uses eight processing elements to meet the speed requirement. The processing rate of the proposed chip can achieve 53 K blocks/s to search from -127 to +127 vectors, using only 8 K gates
Keywords :
VLSI; computational complexity; correlation methods; logic design; motion compensation; motion estimation; search problems; video coding; VLSI; adaptive full-search algorithm; coding bit rate; low-complexity algorithm; motion compensation; motion estimation; processing elements; temporal correlation; video sequences; Adders; Algorithm design and analysis; Bit rate; Computer applications; Kernel; Motion compensation; Motion estimation; Very large scale integration; Video coding; Video sequences;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
DOI :
10.1109/TCSVT.2002.800514