A 7-GHz 1.8-dB NF CMOS low-noise amplifier

Author

Fujimoto, Ryuichi ; Kojima, Kenji ; Otaka, Shoji

Author_Institution

Corporate Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan

Volume

37

Issue

7

fYear

2002

fDate

7/1/2002 12:00:00 AM

Firstpage

852

Lastpage

856

Abstract

A 7-GHz low-noise amplifier (LNA) was designed and fabricated using 0.25-μm CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads were adopted to improve the gain and the noise performance. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. An associated gain of 8.9 dB, a minimum noise figure of 1.8 dB, and an input-referred third-order intercept point of +8.4 dBm were obtained at 7 GHz. The LNA consumes 6.9 mA from a 2.0-V supply voltage. These measured results indicate the feasibility of a CMOS LNA employing these techniques for low-noise and high-linearity applications at over 5 GHz

Keywords

CMOS analogue integrated circuits; amplifiers; integrated circuit noise; 0.25 micron; 1.8 dB; 2.0 V; 6.9 mA; 7 GHz; 8.9 dB; CMOS low-noise amplifier; cascode configuration; dual-gate MOSFET; gain; input-referred third-order intercept point; linearity; minimum noise figure; shielded pad; CMOS technology; Conductivity; Frequency; Low-noise amplifiers; MOSFET circuits; Noise measurement; Noise reduction; Semiconductor device noise; Substrates; Thermal resistance;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.1015682

Filename

1015682