Title :
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability
Author :
Kikukawa, Hirohito ; Tomishima, Shigeki ; Tsuji, Takaharu ; Kawasaki, Toshiaki ; Sakamoto, Shouji ; Ishikawa, Masatoshi ; Abe, Wataru ; Tanizaki, Hiroaki ; Kato, Hiroshi ; Uchikoba, Toshitaka ; Inokuchi, Toshihiro ; Senoh, Manabu ; Fukushima, Yoshifumi ;
Author_Institution :
Adv. LSI Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd, Kyoto, Japan
fDate :
7/1/2002 12:00:00 AM
Abstract :
This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm 2 and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm2 and cell efficiency of 58.1% for the 64-Mb capacity are realized. This core can achieve 230-MHz burst access at 1.0-V power-supply condition by adopting a new data bus architecture: merged shift column redundancy. We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment
Keywords :
DRAM chips; design for testability; embedded systems; integrated circuit testing; large scale integration; logic testing; redundancy; 1 V; 32 Mbit; 64 Mbit; MPEG processing; burn-in test; burst access; cell efficiency; data bus architecture; design for testability; direct memory access; embedded DRAM core; enhanced testability; high efficient redundancy; logic test environment; merged shift column redundancy; power-supply condition; system LSI; two-path testing flow; Analog circuits; Circuit testing; Energy consumption; Large scale integration; Logic circuits; Logic gates; Logic testing; Paper technology; Random access memory; System testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.1015693
