Development and hardware implementation of a compensating algorithm for the secondary current of current transformers

Author

Kang, Y.C. ; Kang, S.H. ; Park, J.K. ; Johns, A.T. ; Aggarwal, R.K.

Author_Institution

Dept. of Electr. Eng., Seoul Nat. Univ., South Korea

Volume

143

Issue

1

fYear

1996

fDate

1/1/1996 12:00:00 AM

Firstpage

41

Lastpage

49

Abstract

The conventional method of dealing with current-transformer (CT) saturation is overdimensioning of the core so that CTs can reproduce up to 20 times the rated current without exceeding 10% ratio correction. However, this not only reduces the sensitivity of relays, as some errors may still be present in the secondary current when a severe fault occurs, but also increases the CT size. An algorithm is described for estimating the secondary current corresponding to the CT ratio under CT saturation using the flux/current (λ/i) curve, and the results of hardware implementation of the algorithm using a digital signal processor are also presented. The main advantage of the algorithm is that it can improve the sensitivity of relays to low-level internal faults, maximise the stability of relays for external faults, and reduce the required CT-core cross-section significantly

Keywords

compensation; current transformers; digital signal processing chips; error analysis; power system protection; relay protection; compensating algorithm; current transformers; current-transformer saturation; digital signal processor; error analysis; external faults; hardware implementation; low-level internal faults; power system protection; relay protection; relay sensitivity; secondary current; severe fault; stability maximisation;

fLanguage

English

Journal_Title

Electric Power Applications, IEE Proceedings -

Publisher

iet

ISSN

1350-2352

Type

jour

DOI

10.1049/ip-epa:19960040

Filename

488213