Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic

Author

Mongkolkachit, Pitsini ; Bhuva, Bharat

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA

Volume

3

Issue

3

fYear

2003

Firstpage

89

Lastpage

92

Abstract

Alpha particles incident on CMOS integrated circuits deposit charges on circuit nodes resulting in single-event transients (SETs). These transient errors propagate through the circuit and reach a latch where they may get latched under proper conditions. This paper presents circuit design techniques to remove the effects of such SET pulses from the circuit. An optimized design is developed whose area, power, and speed performance is superior to other design methods for SET mitigation. Simulation results showing SET pulse elimination are presented.

Keywords

CMOS logic circuits; alpha-particle effects; circuit optimisation; combinational circuits; transients; CMOS integrated circuits; SETs; alpha-particle-induced single-event transients; area; circuit design techniques; circuit nodes; combinational logic; latch; optimized design; power; single-event transients; speed performance; transient errors; Alpha particles; CMOS integrated circuits; CMOS logic circuits; Circuit simulation; Circuit synthesis; Design methodology; Design optimization; Latches; Logic design; Pulse circuits;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2003.816568

Filename

1229723