DocumentCode
777112
Title
Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
Author
Sohi, Gurindar S.
Author_Institution
Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
Volume
39
Issue
3
fYear
1990
fDate
3/1/1990 12:00:00 AM
Firstpage
349
Lastpage
359
Abstract
The problems of data dependency resolution and precise interrupt implementation in pipelined processors are combined. A design for a hardware mechanism that resolves dependencies dynamically and, at the same time, guarantees precise interrupts is presented. Simulation studies show that by resolving dependencies the proposed mechanism is able to obtain a significant speedup over a simple instruction issue mechanism as well as implement precise interrupts
Keywords
interrupts; parallel architectures; pipeline processing; data dependency resolution; instruction issue mechanism; interrupts; pipelined computers; pipelined processors; precise interrupt implementation; Computational modeling; Computer aided instruction; Degradation; Hardware; Helium; Logic; Out of order; Pipelines; Registers; Supercomputers;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.48865
Filename
48865
Link To Document