A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications

Author

Takeda, Koichi ; Hagihara, Yasuhiko ; Aimoto, Yoshiharu ; Nomura, Masahiro ; Nakazawa, Yoetsu ; Ishii, Toshio ; Kobatake, Hiroyuki

Author_Institution

Syst. Devices Res. Labs., NEC Corp., Kanagawa, Japan

Volume

41

Issue

1

fYear

2006

Firstpage

113

Lastpage

121

Abstract

To help overcome limits to the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low-Vth nMOS transistors used to achieve both low-VDD and high-speed operations. For the same speed, the area of our proposed SRAM is 23% smaller than that of a conventional SRAM. Further, we have fabricated a 64-kb SRAM macro using 90-nm CMOS technology and have obtained with it a minimum VDD of 440 mV and a 20-ns access time with a 0.5-V supply.

Keywords

CMOS memory circuits; SRAM chips; high-speed integrated circuits; low-power electronics; 0.5 V; 20 ns; 440 mV; 64 kbit; 90 nm; CMOS technology; high-speed applications; low-VDD applications; nMOS transistors; read-static-noise-margin-free SRAM cell; static random access memory; CMOS logic circuits; CMOS technology; Cache memory; Delay; Dynamic voltage scaling; MOSFETs; Microprocessors; National electric code; Random access memory; Threshold voltage; SRAM scaling; Static random access memory (SRAM); static noise margin;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.859030

Filename

1564351