Title :
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme
Author :
Suzuki, Toshikazu ; Yamagami, Yoshinobu ; Hatanaka, Ichiro ; Shibayama, Akinori ; Akamatsu, Hironori ; Yamauchi, Hiroyuki
Author_Institution :
Memory Technol. Dev. Group, Corp. Syst. LSI Dev. Div., Nagaokakyo, Japan
Abstract :
The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be considered for the low-voltage operation. A hidden error-check-and-correction (HECC) scheme compensated the access time penalty caused by the ECC logic on the output critical path. And a multi-column ECC word assignment (MCE) increased the multi-bit-error immunity while using only 1-bit-correctable ECC which minimized area penalty. A source-level-adjusted direct sense amplifier (SLAD) and a write-replica circuit with an asymmetrical replica memory cell (WRAM) for the device-fluctuation-tolerant access control were also designed. A 130-nm CMOS 32-Kbit SRAM-macro was fabricated with these circuit techniques, which demonstrated: 1) 0.3-V operation with 6.8 MHz; 2) 30-MHz operation which is feasible for mobile use even at 0.4 V, while keeping 960MHz at 1.5 V; and 3) a reduction by 3.6×105 in soft-error rate compared with that of conventional ECC.
Keywords :
CMOS memory circuits; SRAM chips; embedded systems; error correction; low-power electronics; nanoelectronics; radiofrequency integrated circuits; 0.3 V; 0.4 V; 1.5 V; 130 nm; 30 MHz; 32 kbit; 6.8 MHz; 960 MHz; CMOS; ECC circuit implementation; access delay fluctuation; access time penalty; access timing control; asymmetrical replica memory cell; embedded SRAM; hidden error-check-and-correction scheme; multi-bit-error immunity; multi-bit-error-immune hidden-ECC scheme; multi-column ECC word assignment; soft-errors; source-level-adjusted direct sense amplifier; write-replica circuit; Circuits; Delay; Error correction codes; Fluctuations; Frequency; Large scale integration; Random access memory; Redundancy; Timing; Voltage; Access time; ECC; embedded SRAM; fluctuation; low voltage; multi-bit soft error; wide voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.859029