Precise final state determination of mismatched CMOS latches

Author

Van Noije, W.A.M. ; Liu, W.T. ; Navarro, S.J.

Author_Institution

LSI/PEE/EPUSP, Sao Paulo Univ., Brazil

Volume

30

Issue

5

fYear

1995

fDate

5/1/1995 12:00:00 AM

Firstpage

607

Lastpage

611

Abstract

The effect on the metastability of mismatched FET parameters and load capacitances of CMOS latch/flip-flop is analyzed. Theoretical analysis based on small signal devices are provided. From this study we show that the final state depends on both initial voltages and latch mismatches. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semi-planes. This straight line (the metastable line) determines precisely the final latch state, and gives a very good insight about the mismatches which exist in the latch. Several SPICE simulation results are shown for matched/mismatched flip-flops. They agree well with the theoretical ones

Keywords

CMOS logic circuits; SPICE; capacitance; circuit analysis computing; circuit stability; equivalent circuits; flip-flops; transient analysis; SPICE simulation; final state determination; flip-flop; latch mismatches; load capacitances; metastability; mismatched CMOS latches; mismatched FET parameters; small-signal analysis; state diagrams; transient analysis; Circuit noise; Differential amplifiers; Flip-flops; Inverters; Latches; Metastasis; Parasitic capacitance; Semiconductor device modeling; Signal analysis; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.384178

Filename

384178