A MOS approach to CMOS DET flip-flop design

Author

Varma, Pradeep ; Panwar, B.S. ; Chakraborty, Ashutosh ; Kapoor, Dheeraj

Author_Institution

IBM India Res. Lab., Indian Inst. of Technol., New Delhi, India

Volume

49

Issue

7

fYear

2002

fDate

7/1/2002 12:00:00 AM

Firstpage

1013

Lastpage

1016

Abstract

A novel approach to double-edge-triggered (DET) flip-flop design is presented along with a new static flip-flop and a new dynamic flipflop. The approach builds CMOS circuits using pass transistors and MOS-style clocked inverters and addresses issues of threshold voltage drop (V_T drop) and circuit complexity. Among DET designs, the number of switched and total transistors used by our flip-flops is less than or equal to any in related work. Our circuits beat all others in speed (maximum frequency response) by significant margins at medium to high supply voltages. The speed outperformance range for our static flip-flop is 1.5 to 5 V and for our dynamic flip-flop is <2.5 to 5 V

Keywords

CMOS logic circuits; circuit complexity; flip-flops; high-speed integrated circuits; integrated circuit design; logic design; 1.5 to 5 V; CMOS double-edge-triggered flip-flop design; MOS approach; MOS-style clocked inverters; circuit complexity; dynamic flip-flop; maximum frequency response; pass transistors; speed outperformance range; static flip-flop; switched transistors; threshold voltage drop; CMOS technology; Circuits; Clocks; Complexity theory; DH-HEMTs; Flip-flops; Frequency; Inverters; Proposals; Threshold voltage;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/TCSI.2002.800837

Filename

1016835