Path-delay-fault testable nonscan sequential circuits

In this paper we show that any finite state machine can be implemented by a fully path-delay-fault testable nonscan sequential circuit. Synthesis methods are proposed, which use a one-hot encoding of states, a special circuit structure and at most one additional input. Combined with existing synthesis techniques for delay-fault testable combinational circuits, these methods can produce nonscan sequential circuits in which every path has a robust or validatable nonrobust test