A spanning tree carry lookahead adder

Author

Lynch, Thomas ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

Volume

41

Issue

8

fYear

1992

fDate

8/1/1992 12:00:00 AM

Firstpage

931

Lastpage

939

Abstract

The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described. Originally implemented in a 1-μm design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout

Keywords

CMOS integrated circuits; adders; carry logic; integrated logic circuits; trees (mathematics); 56 bit; Advanced Micro Devices; Am29050 microprocessor; CMOS; carry lookahead tree; hybrid carry lookahead-carry select; layout; load distribution; significant adder; spanning tree carry lookahead adder; Added delay; Adders; CMOS logic circuits; CMOS process; Digital arithmetic; Equations; Microprocessors; Process design; Production; Trademarks;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.156535

Filename

156535