DocumentCode :
779069
Title :
Bit-serial systolic divider and multiplier for finite fields GF(2 m)
Author :
Hasan, M. Anwarul ; Bhargava, Vijay K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Volume :
41
Issue :
8
fYear :
1992
fDate :
8/1/1992 12:00:00 AM
Firstpage :
972
Lastpage :
980
Abstract :
A systolic structure for bit-serial division over the field GF(2 m) is developed. Consideration is given to avoid global data communications and dependency of the time step duration on m. This is important for applications where the value of m is large. The divider requires only three basic processors and one simple control signal and its circuit and time complexities are proportional to m2 and m, respectively. It does not depend on the irreducible polynomial and can be expanded easily. Moreover, with m additional simple processors, a bit-serial systolic multiplier is developed which uses part of the divider structure. This is advantageous from the implementation point of view, as both the divider and multiplier can be fabricated on a single chip, resulting in a reduction of area
Keywords :
computational complexity; digital arithmetic; dividing circuits; multiplying circuits; bit-serial division; bit-serial systolic multiplier; chip fabrication; circuit complexity; control signal; finite fields; systolic structure; time complexity; Arithmetic; Circuits; Cryptography; Data communication; Equations; Galois fields; Inverters; Polynomials; Signal processing algorithms; Systolic arrays;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.156540
Filename :
156540
Link To Document :
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