Title :
Low latency time CORDIC algorithms
Author :
Timmermann, Dirk ; Hahn, Helmut ; Hosticka, Bedrich J.
Author_Institution :
Fraunhofer Inst. of Microelectron. Circuits & Syst., Duisburg, Germany
fDate :
8/1/1992 12:00:00 AM
Abstract :
Several methods for increasing the speed of the CORDIC algorithm are presented. First, an improved method which guarantees a constant scale factor when employing redundant addition schemes is developed. Then, an architecture with increased parallelism which considerably reduces the CORDIC latency time and the amount of hardware is described
Keywords :
adders; computational complexity; digital arithmetic; iterative methods; number theory; CORDIC algorithms; constant scale factor; latency time; parallel architecture; redundant addition; Adders; Computer architecture; Delay; Digital arithmetic; Equations; Hardware; Helium; Iterative algorithms; Parallel processing; Vectors;
Journal_Title :
Computers, IEEE Transactions on
