DocumentCode
77925
Title
Predicting Architectural Vulnerability on Multithreaded Processors under Resource Contention and Sharing
Author
Lide Duan ; Lu Peng ; Bin Li
Author_Institution
AMD, Inc., Austin, TX, USA
Volume
10
Issue
2
fYear
2013
fDate
March-April 2013
Firstpage
114
Lastpage
127
Abstract
Architectural vulnerability factor (AVF) characterizes a processor´s vulnerability to soft errors. Interthread resource contention and sharing on a multithreaded processor (e.g., SMT, CMP) shows nonuniform impact on a program´s AVF when it is co-scheduled with different programs. However, measuring the AVF is extremely expensive in terms of hardware and computation. This paper proposes a scalable two-level predictive mechanism capable of predicting a program´s AVF on a SMT/CMP architecture from easily measured metrics. Essentially, the first-level model correlates the AVF in a contention-free environment with important performance metrics and the processor configuration, while the second-level model captures the interthread resource contention and sharing via processor structures´ occupancies. By utilizing the proposed scheme, we can accurately estimate any unseen program´s soft error vulnerability under resource contention and sharing with any other program(s), on an arbitrarily configured multithreaded processor. In practice, the proposed model can be used to find soft error resilient thread-to-core scheduling for multithreaded processors.
Keywords
multi-threading; parallel architectures; processor scheduling; resource allocation; software fault tolerance; software performance evaluation; AVF; architectural vulnerability factor; architectural vulnerability prediction; contention-free environment; coscheduling; first-level model; interthread resource contention; interthread resource sharing; multithreaded processors; performance metrics; processor configuration; processor structure occupancies; processor vulnerability; program soft error vulnerability; scalable two-level predictive mechanism; second-level model; soft error resilient thread-to-core scheduling; Analytical models; Benchmark testing; Instruction sets; Measurement; Predictive models; Training; Hardware reliability; modeling and prediction; modeling of computer architecture;
fLanguage
English
Journal_Title
Dependable and Secure Computing, IEEE Transactions on
Publisher
ieee
ISSN
1545-5971
Type
jour
DOI
10.1109/TDSC.2012.87
Filename
6363442
Link To Document