An evaluation of error performance estimation schemes for DS1 transmission systems carrying live traffic

Under the memoryless binary symmetric channel assumption, the author evaluates performance estimation schemes for DS1 transmission systems carrying live traffic. Bipolar violations, framing bit errors, and code-detected errors are commonly used to estimate bit error ratios and the respective numbers of errored seconds and severely errored seconds that are fundamental parameters in characterizing the performance of DS1 transmission systems. A basic framework based on the coefficient of variation is proposed to evaluate several estimation schemes. Serious drawbacks of the existing estimation schemes based on the superframe (D4) format are identified. A new method for estimating the number of errored seconds is proposed. A computer simulation shows that this proposed method performs much better than the conventional counting method. The performance of the cyclic redundancy check (CRC) code of the extended superframe (ESF) format is also evaluated through the use of a computer simulation model. The simulation results show that all the errored seconds are detected by the CRC code. This is a welcome feature of the code for real-time performance monitoring. Furthermore, the results suggest a new threshold of 326 CRC errors per second for determining severely errored seconds