Modeling and simulation of core switching noise for ASICs

Author

Na, Nanju ; Choi, Jinwoo ; Swaminathan, Madhavan ; Libous, James P. ; O´Connor, Daniel P.

Author_Institution

Agilent Technol., San Jose, CA, USA

Volume

25

Issue

1

fYear

2002

fDate

2/1/2002 12:00:00 AM

Firstpage

4

Lastpage

11

Abstract

This paper presents simulation and analysis of core switching noise for a CMOS ASIC test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations

Keywords

CMOS integrated circuits; application specific integrated circuits; ball grid arrays; capacitors; ceramic packaging; circuit resonance; circuit simulation; frequency-domain analysis; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; power supply circuits; time-domain analysis; ASIC; CBGA; CMOS ASIC test vehicle; PCB; cavity resonator method; ceramic ball grid array package; core switching noise; current edge rates; frequency domain simulations; modeling; off-chip decoupling capacitors; on-chip decoupling capacitors; plane resonances; power supply noise; printed circuit board; simulation; time domain simulations; Analytical models; Application specific integrated circuits; Ceramics; Circuit noise; Circuit simulation; Circuit testing; Electronics packaging; Resonance; Semiconductor device modeling; Vehicles;

fLanguage

English

Journal_Title

Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1521-3323

Type

jour

DOI

10.1109/TADVP.2002.1017678

Filename

1017678