• DocumentCode
    780319
  • Title

    Retiming revisited and reversed

  • Author

    Even, Guy ; Spillinger, I.Y. ; Stok, Leon

  • Author_Institution
    Saarlandes Univ., Saarbrucken, Germany
  • Volume
    15
  • Issue
    3
  • fYear
    1996
  • fDate
    3/1/1996 12:00:00 AM
  • Firstpage
    348
  • Lastpage
    357
  • Abstract
    Retiming is a very promising transformation of circuits which preserves functionality and improves performance. Its benefits are especially promising in automatic synthesis of circuits from higher-level descriptions. However, retiming has not been widely included in current design tools and methodologies. One of the main obstacles is the problem of finding an equivalent initial state for the retimed circuit. In this paper, we introduce a simple modification of the retiming algorithm of Leiserson and Saxe. The modified algorithm helps minimize the effort required to find equivalent initial states and reduces the chance that the network needs to be modified in order to find an equivalent initial state. This algorithm is the kernel of a new efficient retiming method, which searches for optimal retimings while preserving the initial state condition. The paper also presents an improved method to perform the initial state calculation
  • Keywords
    circuit CAD; circuit optimisation; logic CAD; sequential circuits; timing; automatic synthesis; circuit optimisation; circuit transformation; design tools; equivalent initial state; higher-level descriptions; optimal retimings; register relocation; retiming algorithm; sequential circuits; Circuit synthesis; Circuit testing; Delay; Design methodology; Digital signal processing; Kernel; Logic; Microprocessors; Registers; Sequential circuits;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.489105
  • Filename
    489105