A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor

Author

Dae-Hyun Kwon ; Young-Seok Park ; Woo-Young Choi

Author_Institution

Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

Volume

62

Issue

6

fYear

2015

fDate

Jun-15

Firstpage

1472

Lastpage

1480

Abstract

We demonstrate a clock and data recovery (CDR) circuit having a new type of a multi-level bang-bang phase detector (ML-BBPD). The gain characteristics of our ML-BBPD can be programmed by scanning the dead-zone width of a variable dead-zone BBPD in the time domain. Its linear-like gain characteristics result in less sensitive CDR performance against input jitter and process, voltage, and temperature (PVT) variations. In addition, a built-in on-chip jitter monitor can be easily implemented using our ML-BBPD. A prototype 1.25-Gb/s CDR based on our ML-BBPD with a built-in jitter monitor is realized with 0.18- μm CMOS technology and its performance is successfully verified with measurement.

Keywords

CMOS integrated circuits; clock and data recovery circuits; jitter; phase detectors; programmable circuits; time-domain analysis; CDR circuit; CMOS technology; ML-BBPD; PVT variation; built-in on-chip jitter monitor; clock and data recovery circuit; complementary metal oxide semiconductor; dead-zone width; linear-like gain characteristic; process voltage temperature variation; programmable multilevel bang-bang phase detector characteristic; size 0.18 mum; time domain; Clocks; Detectors; Generators; Jitter; Monitoring; Temperature measurement; Voltage-controlled oscillators; Clock and data recovery circuit; multi-level bang-bang phase detector; on-chip jitter monitoring;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2015.2415180

Filename

7112583