• DocumentCode
    780804
  • Title

    Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond

  • Author

    Johnson, Jeffrey B. ; Hook, Terence B. ; Lee, Yoo-Mi

  • Author_Institution
    Semicond. R&D Center, IBM Microelectron., Essex Junction, VT
  • Volume
    29
  • Issue
    7
  • fYear
    2008
  • fDate
    7/1/2008 12:00:00 AM
  • Firstpage
    802
  • Lastpage
    804
  • Abstract
    This letter investigates random dopant fluctuation transistor mismatch. The dominance of the halo implant is demonstrated experimentally and with simulation, and a compact model form is developed for improved representation of the phenomenon.
  • Keywords
    CMOS integrated circuits; ion implantation; transistors; CMOS integrated circuit; halo implant; random dopant fluctuation; size 65 nm; threshold voltage mismatch; transistor mismatch; CMOS technology; Circuit simulation; Fluctuations; MOSFET circuits; Microelectronics; Research and development; Resource description framework; Semiconductor device modeling; Semiconductor process modeling; Threshold voltage; CMOSFETs; doping; transistors;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2008.2000649
  • Filename
    4558100
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=780804