Modeling and analysis for optimal PVR implementation

This paper presents a new methodology of modeling and analyzing required elements to design an HD-DTV PVR (high definition digital television personal video recorder) with efficient architecture. The bits modeling method is based on the RMS (rate monotonic scheduling) algorithm and provides a convenient way to predict the performance of real-time PVR systems and to modify its architecture with optimal resources. From the analysis, we could design PVR whose real-time performance is verified. We also developed time-shifter ASIC chip that is in charge of manipulating HD streams to support various functions like trick-mode play in the PVR