A scalable high-speed current-mode winner-take-all network for VLSI neural applications

Author

Smedley, Sean ; Taylor, John ; Wilby, Mark

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. Coll. London, UK

Volume

42

Issue

5

fYear

1995

fDate

5/1/1995 12:00:00 AM

Firstpage

289

Lastpage

291

Abstract

This paper describes a very flexible, high-speed current-mode winner-take-all network (WTA) for use in artificial neural systems. Since the WTA is based on a network of identical current switching cells requiring only adjacent transistor matching, it is particularly suited to use in large systems. In addition, since the network is based on a tree structure, very little space is occupied by interconnect, thus ensuring a very compact layout. This WTA has current (matching score) inputs and provides a buffered, binary encoded voltage output

Keywords

BiCMOS integrated circuits; VLSI; neural chips; VLSI neural applications; WTA network; adjacent transistor matching; artificial neural systems; buffered binary encoded voltage output; compact layout; current switching cells; current-mode network; scalable high-speed network; tree structure; winner-take-all network; Artificial neural networks; CMOS technology; Encoding; Flexible printed circuits; Impedance matching; Integrated circuit interconnections; MOSFETs; Tree data structures; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.386164

Filename

386164