Title :
Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications
Author :
Sharaf, K.M. ; Elmasry, M.I.
Author_Institution :
VLSI Res. Group, Waterloo Univ., Ont., Canada
fDate :
6/1/1995 12:00:00 AM
Abstract :
A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 μm BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4× improvement in the load driving capability and 3.4× improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV
Keywords :
BiCMOS logic circuits; combinational circuits; 0.6 micron; NMOS emitter-follower stage; active-pull-down nonthreshold logic; first-order analysis; high-speed low-power applications; nonthreshold logic BiCMOS circuits; BiCMOS integrated circuits; Circuit simulation; Degradation; Energy consumption; Inverters; Logic circuits; Logic gates; MOS devices; Power dissipation; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
