High-speed low-power cross-coupled active-pull-down ECL circuit

Author

Chuang, C.T. ; Wu, B. ; Anderson, C.J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

30

Issue

6

fYear

1995

fDate

6/1/1995 12:00:00 AM

Firstpage

701

Lastpage

705

Abstract

This paper presents a high-speed low-power cross-coupled active-pull-down ECL (CC-APD-ECL) circuit. The circuit features a cross-coupled active-pull-down scheme to improve the power-delay of the emitter-follower stage. The cross-coupled biasing scheme preserves the emitter-dotting capability and requires no extra biasing circuit branch and power for the active-pull-down transistor. Based on a 0.8 μm double poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.7× improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay, 2.1× improvement in the load driving capability, and 3.5× improvement in the dotting delay penalty compared with the conventional ECL circuit. The design considerations of the circuit are discussed

Keywords

bipolar logic circuits; delays; emitter-coupled logic; 0.8 micron; active-pull-down ECL circuit; cross-coupled ECL circuit; cross-coupled biasing scheme; dotting delay penalty; double poly self-aligned bipolar technology; emitter-dotting capability; emitter-follower stage; high-speed operation; low-power operation; power-delay improvement; Capacitors; Coupling circuits; Delay; Energy consumption; Logic circuits; Logic devices; Solid state circuit design; Steady-state; Switches; Virtual manufacturing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.387076

Filename

387076