Energy-efficient static sparse-tree adder based on MUX-less bypassing architecture

An energy-efficient 64 bit static sparse-tree adder using a multiplexer (MUX)-less bypassing scheme is proposed for mobile central processing units. Conventionally, bypassing schemes have been used to eliminate unnecessary switching of circuits but have incorporated a large delay overhead due to their output MUX, which reduces the energy efficiency of circuits in terms of power-delay product (PDP). A novel static sparse-tree adder is presented based on a proposed MUX-less bypassing scheme to reduce the delay associated with the conventional bypassing scheme, thereby improving the energy efficiency, i.e. the PDP. Simulation results show a 30% reduction in PDP compared to the conventional bypassing adder and a 13% reduction from the state-of-the-art technique.