A mixed-signal VLSI neuroprocessor for image restoration

Author

Lee, Ji-Chien ; Sheu, Bing J. ; Choi, Joongho ; Chellappa, Rama

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

2

Issue

3

fYear

1992

fDate

9/1/1992 12:00:00 AM

Firstpage

319

Lastpage

324

Abstract

An analog systolic architecture that uses multiple neuroprocessors for image restoration is presented. For a two-dimensional image, parallel processing is performed for different rows of pixel data and pipelined processing is performed on each row of pixel data. For the image restoration neuroprocessor, local data computation is executed by analog circuitry to achieve full parallelism and to minimize power dissipation. Interprocessor communication is carried out in the digital format to maintain strong signal strength across the chip boundary and to allow multichip operation for high-speed image processing

Keywords

VLSI; computerised picture processing; digital signal processing chips; neural nets; pipeline processing; systolic arrays; VLSI neuroprocessor; analog circuitry; analog systolic architecture; high-speed image processing; image restoration; interprocessor communication; local data computation; multiprocessor design; parallel processing; pipelined processing; power dissipation; signal strength; two-dimensional image; Analog computers; Circuits; Computer architecture; Concurrent computing; Image restoration; Parallel processing; Pixel; Power dissipation; Signal processing; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.157164

Filename

157164