Title :
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
Author :
Zhang, Kevin ; Bhattacharya, Uddalak ; Chen, Zhanping ; Hamzaoglu, Fatih ; Murray, Daniel ; Vallepalli, Narendra ; Wang, Yih ; Zheng, B. ; Bohr, Mark
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fDate :
4/1/2005 12:00:00 AM
Abstract :
A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-μm2 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5× while maintaining the integrity of stored data.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit design; leakage currents; low-power electronics; memory architecture; 0.7 V; 65 nm; 6T SRAM cell; 70 Mbit; CMOS technology; SRAM design; SRAM leakage; built-in programmable defect screen circuit; dynamic sleep transistor; integrated leakage reduction scheme; noise margin; process skew; programmable bias transistors; voltage control; weak-write test mode; CMOS technology; Circuit stability; Degradation; Design optimization; Integrated circuit technology; Power supplies; Random access memory; Sleep; Very large scale integration; Voltage control; Leakage reduction; SRAM; sleep transistor; weak-write test mode;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.842846
