Title :
Low complexity architecture for exponentiation in GF(2m)
Author :
Hasan, M. Anwar ; Bhargava, V.K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Abstract :
A pipeline bit-serial multiplier architecture for the Galois field GF(2m) is presented. A structure for finite field exponentiation is developed based on the multiplier. The structure is regular, area efficient and suitable for VLSI implementation for large fields.
Keywords :
cryptography; digital arithmetic; multiplying circuits; parallel architectures; pipeline processing; GF(2 m); Galois field; VLSI implementation; cryptosystem; finite field exponentiation; pipeline bit-serial multiplier architecture;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19921272
