• DocumentCode
    787168
  • Title

    On over-the-cell channel routing with cell orientations consideration

  • Author

    Her, T.W. ; Wong, D.F.

  • Author_Institution
    Mentor Graphics Corp., San Jose, CA, USA
  • Volume
    14
  • Issue
    6
  • fYear
    1995
  • fDate
    6/1/1995 12:00:00 AM
  • Firstpage
    766
  • Lastpage
    772
  • Abstract
    Existing over-the-cell channel routers assume that the orientations of the cells are fixed. In practice, it is quite common that each cell can be horizontally flipped. This pin rearrangement flexibility should be used by over-the-cell routers to further reduce channel routing area. Given a placement of cells in multiple rows with pin terminals at the top and bottom edges of the cells and each cell can be flipped. The objective is to select an orientation for each cell and a set of net segments to be routed over the cells such that the final routing area is minimized. In this paper, we assume the HCVD cell model, i.e., power/ground buses run through the middle of each cell row horizontally and one layer is available for over-the-cell routing. For this model, it suffices to focus on over-the-cell routing for each individual cell row. We present a branch-and-bound optimal algorithm to maximize the total weight of the net segments to be routed in both upper and Lower over-the-cell regions. With minor modifications, our algorithm is applicable to simultaneously consider pin assignment and over-the-cell routing. The proposed algorithm has been implemented and tested on a set of industrial examples. Reduction in total channel densities of up to 37% was obtained using a reasonable amount of CPU time
  • Keywords
    VLSI; circuit layout CAD; integrated circuit layout; network routing; CPU time; HCVD cell model; VLSI design; branch/bound optimal algorithm; cell orientations; cell placement; channel density reduction; channel routers; net segments; over-the-cell channel routing; pin assignment; pin rearrangement flexibility; pin terminals; routing area minimisation; Computer graphics; Routing; Testing; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.387737
  • Filename
    387737