Title :
Delay-testable implementations of symmetric functions
Author :
Ke, Wuudiann ; Menon, P.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
We show that most symmetric functions do not have delay-testable two-level implementations. A method of transforming any untestable minimal two-level implementation of a symmetric function into a delay-testable three- or four-level one using the distributive law is presented
Keywords :
combinational circuits; delays; fault diagnosis; logic testing; symmetric switching functions; delay-testable implementations; distributive law; symmetric functions; two-level implementation transformation; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay effects; Minimization; Propagation delay; Robustness; Sampling methods; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
