• DocumentCode
    787176
  • Title

    Delay-testable implementations of symmetric functions

  • Author

    Ke, Wuudiann ; Menon, P.R.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
  • Volume
    14
  • Issue
    6
  • fYear
    1995
  • fDate
    6/1/1995 12:00:00 AM
  • Firstpage
    772
  • Lastpage
    775
  • Abstract
    We show that most symmetric functions do not have delay-testable two-level implementations. A method of transforming any untestable minimal two-level implementation of a symmetric function into a delay-testable three- or four-level one using the distributive law is presented
  • Keywords
    combinational circuits; delays; fault diagnosis; logic testing; symmetric switching functions; delay-testable implementations; distributive law; symmetric functions; two-level implementation transformation; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay effects; Minimization; Propagation delay; Robustness; Sampling methods; Timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.387738
  • Filename
    387738
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=787176