Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

Author

Chen, Xiangdong ; Ouyang, Qiqing Christine ; Wang, Geng ; Banerjee, Sanjay K.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

Volume

49

Issue

11

fYear

2002

fDate

11/1/2002 12:00:00 AM

Firstpage

1962

Lastpage

1968

Abstract

Graded doping profile in the channel of vertical sub-100-nm nMOSFETs was investigated in this study. Conventional single-step ion implantation was used to form the asymmetric graded doping profile in the channel. No large-angle-tilt implant is needed. The device processing is compatible with conventional CMOS technology. In a graded-channel-doping device, with the higher doping near the source, drain induced barrier lowering (DIBL) and the off-state leakage current are reduced significantly. The graded doped channel also has a lower longitudinal electric field near the drain. Therefore, hot-carrier related reliability is improved substantially with this type of device structure.

Keywords

MOSFET; doping profiles; hot carriers; ion implantation; leakage currents; semiconductor device models; semiconductor device reliability; 100 nm; CMOS compatible device processing; DIBL reduction; asymmetric graded doping profile; device simulation; drain induced barrier lowering; graded channel doping; hot-carrier reliability improvement; n-channel MOSFETs; off-state leakage current reduction; short-channel effects; short-channel performance improvement; single-step ion implantation; vertical nMOSFETs; CMOS process; CMOS technology; Computational modeling; Doping profiles; Hot carriers; Implants; Leakage current; MOSFETs; Medical simulation; Microelectronics;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2002.804697

Filename

1097913