BIST of PCB interconnects using boundary-scan architecture

Author

Hassan, Abu S M ; Agarwal, V.K. ; Nadeau-Dostie, Benoit ; Rajski, Janusz

Author_Institution

Bell Northern Res., Ottawa, Ont., Canada

Volume

11

Issue

10

fYear

1992

fDate

10/1/1992 12:00:00 AM

Firstpage

1278

Lastpage

1288

Abstract

The issues of printed circuit board (PCB) interconnect testing are addressed in the context of boundary-scan architecture. Boundary-scan architecture is treated here as the framework for a PCB level built-in self-test (BIST). A novel BIST method is developed which utilizes various features of the architecture. Boundary-scan architecture is shown to have the capability to generate time-efficient test vector sets. Response compaction within the boundary-scan chain is introduced to reduce shift out time as well as to simplify detection and diagnosis. However, the proposed BIST schemes require some extensions of the standard boundary-scan cells, and the schemes can work only if every boundary-scan cell of every IC on the PCB has the proposed extensions

Keywords

automatic testing; boundary scan testing; built-in self test; printed circuit testing; BIST; PCB interconnects; boundary-scan architecture; built-in self-test; interconnect testing; printed circuit board; response compaction; time-efficient test vector sets; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Compaction; Integrated circuit interconnections; Pins; Printed circuits; Shift registers;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.170990

Filename

170990