Two-level switching pattern deadbeat DSP controlled PWM inverter

Author

Hua, Chihchiang

Author_Institution

Dept. of Electr. Eng., Nat. Yunlin Inst. of Technol., Taiwan, China

Volume

10

Issue

3

fYear

1995

fDate

5/1/1995 12:00:00 AM

Firstpage

310

Lastpage

317

Abstract

A two-level switching algorithm of the deadbeat controlled PWM inverter is presented. Two levels, instead of three levels, are used in the pulse pattern. This scheme allows the use of higher switching frequency for a given computation time delay, which results in lower total harmonic distortion (THD) at the output. Control algorithms are derived. The proposed control scheme is implemented using a TI TMS320C14 DSP controlling an inverter to produce a very low THD sinusoidal output voltage. Simulation and experimental results are presented to verify the performance

Keywords

PWM invertors; digital control; digital signal processing chips; harmonic distortion; power system harmonics; simulation; switching circuits; TI TMS320C14 DSP; computation time delay; control algorithms; deadbeat DSP controlled PWM inverter; inverter; performance verification; simulation; total harmonic distortion; two-level switching algorithm; very low THD sinusoidal output voltage; Computational modeling; Control systems; Delay effects; Digital signal processing; Power semiconductor switches; Pulse width modulation; Pulse width modulation inverters; Signal processing algorithms; Switching frequency; Voltage control;

fLanguage

English

Journal_Title

Power Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0885-8993

Type

jour

DOI

10.1109/63.387996

Filename

387996