DocumentCode :
790298
Title :
A wide-range delay-locked loop with a fixed latency of one clock cycle
Author :
Chang, Hsiang-Hui ; Lin, Jyh-Woei ; Yang, Ching-Yuan ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
37
Issue :
8
fYear :
2002
fDate :
8/1/2002 12:00:00 AM
Firstpage :
1021
Lastpage :
1027
Abstract :
A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N×TDmax) to 1/(3TDmin), where TDmin and TDmax are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 μm single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 μm×515 μm and consumes a maximum power of 132 mW at 130 MHz.
Keywords :
CMOS analogue integrated circuits; delay lock loops; timing jitter; 0.35 micron; 132 mW; 6 to 130 MHz; CMOS process; delay-locked loop; fixed latency; harmonic locking; jitter; phase selection circuit; start-controlled circuit; wide-range operation; CMOS process; Circuits; Clocks; Delay effects; Delay lines; Frequency synchronization; Jitter; Phase locked loops; Time measurement; Very large scale integration;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2002.800922
Filename :
1020241
Link To Document :
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