DocumentCode :
790335
Title :
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
Author :
Ker, Ming-Dou ; Chuang, Chien-Hui
Author_Institution :
Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
37
Issue :
8
fYear :
2002
fDate :
8/1/2002 12:00:00 AM
Firstpage :
1046
Lastpage :
1055
Abstract :
A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35 μm CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original ∼2 kV to >8 kV by using this proposed ESD protection circuit.
Keywords :
CMOS integrated circuits; buffer circuits; electrostatic discharge; protection; thyristors; 0.35 micron; 2 to 8 kV; CMOS IC; ESD clamp device; electrostatic discharge protection circuit; gate-coupling circuit technique; gate-oxide reliability; human-body-model; mixed-voltage I/O buffer; stacked-nMOS triggered silicon controlled rectifier; CMOS process; Clamps; Electrostatic discharge; Integrated circuit technology; Laboratories; Leakage current; MOS devices; Protection; Thyristors; Voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2002.800933
Filename :
1020244
Link To Document :
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