Highly suppressed boron penetration in NO-nitrided SiO/sub 2/ for p/sup +/-polysilicon gated MOS device applications

Author

Han, L.K. ; Wristers, D. ; Yan, J. ; Bhat, M. ; Kwong, D.L.

Author_Institution

Microelectron. Res. Center, Texas Univ., Austin, TX, USA

Volume

16

Issue

7

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

319

Lastpage

321

Abstract

In this paper, we demonstrate the superior diffusion barrier properties of NO-nitrided SiO/sub 2/ in suppressing boron penetration for p/sup +/-polysilicon gated MOS devices. Boron penetration effects have been studied in terms of flatband voltage shift, decrease in inversion capacitance (due to polysilicon depletion effect), impact on interface state density, and charge-to-breakdown. Results show that NO-nitrided SiO/sub 2/, as compared to conventional thermal SiO/sub 2/, exhibits much higher resistance to boron penetration, and therefore, is very attractive for surface channel PMOS technology.<>

Keywords

MOSFET; diffusion barriers; electric breakdown; elemental semiconductors; interface states; nitridation; rapid thermal processing; semiconductor-insulator boundaries; silicon; NO; SiO/sub 2/-Si; boron penetration effects; charge-to-breakdown; diffusion barrier properties; flatband voltage shift; interface state density; inversion capacitance; p/sup +/-polysilicon gated MOS device; polysilicon depletion effect; surface channel PMOS technology; Boron; CMOS technology; Capacitance; Capacitance-voltage characteristics; Interface states; MOS devices; MOSFET circuits; Nitrogen; Rapid thermal processing; Thermal resistance;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.388720

Filename

388720