Title :
A single-chip programmable platform based on a multithreaded processor and configurable logic clusters
Author :
Bae, Young-Don ; Park, Seong-Il ; Park, In-Cheol
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Abstract :
This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm2 prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-μm CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.
Keywords :
CMOS digital integrated circuits; SRAM chips; embedded systems; field programmable gate arrays; integrated circuit design; multi-threading; reduced instruction set computing; system-on-chip; 100 MHz; 3.3 V; 32 bit; 32-bit multithreaded RISC processor; 370 mW; 8 kB; CMOS technology; IP-based design; clock frequency; configurable logic clusters; control circuitry; embedded system chips; external interface functions; four metal layers; four-threaded MT-RISC; hardware thread scheduling unit; high-level language-based designs; multithreaded processor; on-chip SRAM; on-chip memories; power consumption; programmable FIFO memories; rapid thread switch; single-chip programmable platform; system-on-chip design; CMOS technology; Embedded system; Hardware; Logic circuits; Logic design; Processor scheduling; Programmable control; Reduced instruction set computing; Switches; Yarn;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.817259