DocumentCode
794082
Title
An implicit path-delay fault diagnosis methodology
Author
Padmanaban, Saravanan ; Tragoudas, Spyros
Author_Institution
Comput. Sci. & Electr. Eng. Dept., Univ. of Maryland, Baltimore, MD, USA
Volume
22
Issue
10
fYear
2003
Firstpage
1399
Lastpage
1408
Abstract
The first nonenumerative framework for diagnosing path delay faults (PDFs) using zero suppressed binary decision diagrams is introduced. We show that fault-free PDFs with certain validated nonrobust test may be used together with fault-free robustly tested faults to eliminate faults from the set of suspected faults. All operations are implemented by an implicit diagnosis tool based on the zero-suppressed binary decision diagram. The proposed method is space and time nonenumerative as opposed to existing methods which are space and time enumerative. Experimental results on the ISCAS´85 benchmarks show that the proposed technique is on average three times more efficient than the existing techniques.
Keywords
automatic testing; binary decision diagrams; delays; fault diagnosis; logic testing; ISCAS´85 benchmarks; implicit diagnosis tool; implicit path-delay fault diagnosis methodology; nonenumerative framework; validated nonrobust test; zero-suppressed binary decision diagram; Boolean functions; Circuit faults; Circuit testing; Data structures; Delay effects; Fault diagnosis; Integrated circuit testing; Performance evaluation; Space technology; Timing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2003.818132
Filename
1233825
Link To Document