The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences

Author

Chen, Tao ; Gielen, Georges G E

Author_Institution

ESAT-MICAS, Katholieke Univ. Leuven, Heverlee, Belgium

Volume

53

Issue

1

fYear

2006

Firstpage

3

Lastpage

15

Abstract

For a high-accuracy current-steering digital-to-analog converters (DACs), the delay differences between the current sources is one of the major reasons that cause bad dynamic performance. In this paper, a mathematical model describing the impact of the delay differences on the DACs SFDR property is presented. The results are verified by comparison to behavioral-level simulations and to actual measurement data from published papers. Based on this analysis, the delay differences cancellation (DDC) technique to reduce the impact of the delay differences on the SFDR property is proposed and verified by simulation results.

Keywords

delays; digital-analogue conversion; behavioral-level simulations; cell-dependent delay differences; current-steering DAC; delay differences cancellation; delay distribution; digital-to-analog converters; dynamic SFDR; spurious-free dynamic range; switch-and-latch cell; switching sequence; Analytical models; CMOS technology; Clocks; Delay; Digital-analog conversion; Dynamic range; Impedance; Mathematical model; Switches; Voltage; Current-steering digital-to-analog converters (DACs); delay difference; delay differences cancellation (DDC); delay distribution; spurious-free dynamic range (SFDR); switch-and-latch cell; switching sequence;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2005.854409

Filename

1576881